The present invention is related to integrated circuits and their fabrication. More specifically, the invention relates to a structure and method of fabricating a conductor line (e.g. gate conductor, wordline, etc.) for improving process tolerances in providing borderless contacts.
As described below, the present invention is directed to forming an improved conductor line structure of an integrated circuit (IC) which provides increased process tolerance for forming a borderless contact to a semiconductor substrate. The present invention is especially well-suited for fabrication of wordlines and borderless bitline contacts of a dynamic random access memory (DRAM).
Dynamic random access memories (DRAMs) include very densely packed arrays of semiconductor devices which are accessed by wordlines running in a first horizontal direction over the major surface of a substrate, and a set of bitlines which run in a second horizontal direction over the major surface of the substrate. In a typical DRAM, a wordline is activated by raising its voltage to access a row of storage cells of a data storage array. When a particular row is accessed by an activated wordline, a bitline is used to read a data bit signal of a storage cell of that accessed row. This is done by transferring a charge stored in the storage cell to a sense amplifier. A bitline is used to write a data bit signal of a storage cell of the accessed row by transferring and storing a charge from the sense amplifier to the storage cell. Storage cells of a DRAM require periodic refreshing to avoid loss of the data stored therein. To refresh a storage cell, the bitline transfers the charge stored in the storage cell to the sense amplifier, amplifies it there to a desirable level, and then rewrites the storage cell with the same data by transferring the amplified charge back to the storage cell.
In many DRAMs, wordlines have an encapsulated structure including a linearly extending conductor and an insulative structure encapsulating the top and sidewalls of the conductor. The insulative structure typically includes an insulating cap and insulating spacers. Silicon nitride is a typical material for providing an insulating cap. Silicon nitride and/or silicon dioxide are typically used for providing insulating spacers. The linearly extending conductor generally includes heavily doped polysilicon and/or one or more metals and/or one or more compounds of metals, especially metal silicides. One or more barrier layers and/or adhesion layers may also be included within the conductor for enhancing performance.
DRAMs having high integration density typically require wordlines to be encapsulated to support tight wordline pitch. Tight wordline pitch is also needed for best signal transfer on bitlines, because bitlines are shorter when wordlines have tight pitch, and shorter bitlines have less parasitic capacitance to interfere with signal transfer. When wordlines are spaced very close together, i.e. at any spacing less than about 1½ times the minimum lithographic feature size or spacing (F) for the technology, the bitline contacts must be self-aligned to the insulative material which encapsulates the wordlines. The wordline to wordline spacing is typically set to the minimum spacing of 1 F, i.e. at the critical dimension. Because of difficulties in achieving perfect alignment between the critical dimensioned bitline contact mask and the underlying critical dimensioned pattern, the minimum sized holes (of 1 F size) that are etched to form the bitline contacts would be subject to landing on tops and/or sidewalls of the conductive wordlines. The bitline contacts formed by depositing a conductive material in the contact holes would then short circuit to the wordlines. Hence, wordlines must have conductors which are encapsulated both on their sides and top to prevent such shorting. Bitline contacts are then formed between such encapsulated wordlines which are self-aligned to the opening between the insulative material that encapsulates the wordlines.
Such self-aligned process for forming bitline contacts between encapsulated wordlines is known as a borderless bitline contact process. Some processes for forming borderless bitline contacts are described in U.S. Pat. Nos. 6,319,840 and 6,261,933. As described in U.S. Pat. No. 6,319,840, a bitline contact is formed in a self-aligned manner between two encapsulated wordlines. As used herein, the term “horizontal” means any direction which is parallel to the major surface of a semiconductor substrate, whereas “vertical” means a direction which is perpendicular to that major surface. As shown in that patent in FIG. 1A, a plurality of patterned conductive lines 14 are provided which run in a first horizontal direction over a major surface 11 of a single-crystal semiconductor region of a substrate 10. Conductive lines 14 can be both wordlines and gate conductors of a memory array, when the channel regions of transistors of the memory array are located below a layer 12 of gate dielectric and oriented in a direction parallel to the major surface of the substrate. Alternatively, the conductive lines 14 can be merely wordlines of a memory array, as connected to gate conductors of transistors having vertically oriented channels formed below the major surface of the substrate. In such case, layer 12 may be used as an array top oxide rather than a gate dielectric. Each patterned conductor line 14 includes sidewall spacers 16 that are formed on each side of the patterned conductive line.
To form the borderless bitline contact, a contact hole is first etched in a dielectric region between two wordlines 14 to reach the single-crystal semiconductor region 10 below the wordlines. The etch process is generally but not completely selective to the material of the insulating sidewall spacers 16 and the insulating cap 18 that together encapsulate the wordline. Thereafter, heavily doped polysilicon is deposited in contact with the exposed single-crystal silicon to form a borderless bitline contact that is self-aligned to the encapsulated wordlines.
As the chip area occupied by a DRAM is reduced from one technology generation to the next, the minimum lithographic feature size F (equivalent to minimum spacing) is also reduced such that there is less space available for accommodating both the bitline contact and the sidewall spacers disposed to the sides of the bitline contact.
It is apparent that there is a minimum thickness for the sidewall spacers formed on the conductor line, below which poor results are obtained. While the bitline contact holes are formed by etching selectively to the material of the spacers, the selectivity is not complete, such that the thickness of the spacer is reduced somewhat during the etch. If the resulting sidewall spacers become too thin, then capacitance between the wordline and bitline can increase up to several times the desired maximum capacitance, which degrades the quality of the bitline signal. If a spacer becomes thinned, i.e., etched through, to the point that the bitline comes in conductive contact with the wordline, the bitline will short circuit to the wordline.
FIG. 1B is a cross-sectional diagram illustrating this problem. When the minimum feature size F for lithographically patterning structures of a DRAM is decreased below 100 nm, the thickness of spacers 116 can be too thin to prevent undesired conductive contact between metal layers 114 of wordlines having width of the minimum feature size F and the bitline contact 132. Such undesired contact causes a short circuit between the particular wordline and the bitline, causing at least the bitline to become inoperative and, often the wordline as well (depending on the technique used for bitline sparing). The most probable location for the undesired contact to occur is the top corner 134.
On the other hand, it is apparent that there is little tolerance for increasing the thickness of the sidewall spacers. When the sidewall spacers are too thick, poor contact (highly resistive) or nonexistent contact will be made between the bitline contact and the drain of the transistor that is formed in the single-crystal semiconductor region 110 of the substrate. Such condition, known as “bitline contact open” must be avoided.
The thickness of the sidewall spacer is also limited for other reasons. In addition to the memory array, every DRAM, including standalone DRAMs and DRAMs which are embedded in chips having additional function, e.g. a processor, includes other “support” transistors which are optimized for certain performance such as switching, drive and/or gain. The sidewall spacers of transistors in the memory array are formed at the same time and by the same process as the sidewall spacers of such support transistors. The support transistors require the sidewall spacers to remain relatively thin for performance reasons. For one, the sidewall spacers need to relatively thin in order to allow implants and other processes to be performed in close proximity to the channel regions of the transistors.
The spacer thickness is a very important process parameter for planar device performance. The spacer thickness affects the threshold voltage, leakage current, and drive current of planar transistors, e.g. planar passgate transistors for the memory cell array and support circuit devices. The sidewall spacers cannot be thickened in the memory cell array without impacting the performance of support transistors. Accordingly, the sidewall spacer thickness must be maintained within the tolerances for fabricating the support transistors.
FIG. 2 illustrates one approach for addressing the possibility of shorting between wordline and bitline contact. The approach described here is background to the present invention but is not admitted to be prior art. In this approach, an upper (metallic or metal compound) layer or layers 214 of the conductor line stack is defined as a narrower structure than the lowest layer 215, which is composed of a different material such as doped polysilicon. In such approach, the conductive stack including the lowest layer 215 and the upper layer 214 can be formed by photolithographically patterning a resist layer to have 1 F width, and then performing a vertical etch, such as a reactive ion etch (RIE), stopping on the underlying oxide layer 212. A subsequent process can then be performed, such as a mask open process to first thin the profile of the insulating cap 218 and then etch the upper layer 214 selective to the polysilicon of the lowest layer 215, to decrease the width of the upper layer 214.
However, this approach leaves much to be desired. When the upper layer of the wordline line is made narrower, higher resistance results because the portion of the wordline containing the metal(s) and/or metal compound(s) has smaller cross-sectional area. The higher resistance causes higher propagation delay along the wordline, which degrades the speed of the circuit. A second problem is that the performance of memory array transistors coupled to the wordline is sensitive to the thickness of the spacers 220. As described above, the sidewall spacer cannot be thickened without limit, in order to avoid affecting the performance of the support transistors. Rather, the sidewall spacer thickness must be maintained within the tolerances provided therefor, and little margin is provided for variation.
In view of the foregoing, it would be desirable to provide a structure and method of forming a conductor line which improves process tolerance for forming borderless bitline contacts.
It would further be desirable to provide a structure and method of forming a conductor line having a layer including a metal and/or metal silicide which provides improved process tolerance while maintaining resistance tolerably low.